US 12,449,830 B2
High voltage input low dropout regulator circuit
Alexandru-Valentin Craescu, Buchare (RO)
Assigned to Microchip Technology Incorporated, Chandler, AZ (US)
Filed by Microchip Technology Incorporated, Chandler, AZ (US)
Filed on Oct. 20, 2022, as Appl. No. 17/970,033.
Claims priority of provisional application 63/322,869, filed on Mar. 23, 2022.
Prior Publication US 2023/0305585 A1, Sep. 28, 2023
Int. Cl. G05F 1/563 (2006.01); G05F 1/56 (2006.01); G05F 1/575 (2006.01)
CPC G05F 1/563 (2013.01) [G05F 1/561 (2013.01); G05F 1/575 (2013.01)] 10 Claims
OG exemplary drawing
 
1. An low dropout (LDO) regulator circuit comprising:
a pre-regulator circuit to receive a high voltage input voltage and provide a low voltage supply voltage; and
an LDO regulator to receive the low voltage supply voltage and provide a low voltage output voltage;
wherein the pre-regulator circuit comprises an input stage, an output stage coupled to the input stage, and a first MOSFET coupled to the output stage to provide the low voltage supply voltage, wherein the input stage, output stage, and first MOSFET receive the high voltage input voltage;
wherein the LDO regulator comprises a second MOSFET to receive the low voltage supply voltage and provide the low voltage output voltage;
wherein the first MOSFET is a high voltage n-type MOSFET and the second MOSFET is a low voltage p-type MOSFET;
wherein a source terminal of the first MOSFET is coupled to a source terminal of the second MOSFET, the low voltage supply voltage is provided at terminal of the first MOSFET, and the low voltage output voltage is provided at a drain terminal of the second MOSFET;
wherein the LDO regulator comprises a first amplifier and a second amplifier, to respectively receive the low voltage supply voltage;
wherein the first amplifier comprises an inverting input to receive a representation of the low voltage output voltage and a non-inverting input to receive a reference voltage;
wherein the second amplifier comprises a non-inverting input to receive an output of the first amplifier, and an inverting input to receive the low voltage output voltage; and
wherein the output of the second amplifier is coupled to gate terminal of the second MOSFET.