US 12,449,478 B2
Low overhead loop back test for high speed transmitter
Rupesh Singh, Ghaziabad (IN); and Ankur Bal, Greater Noida (IN)
Assigned to STMicroelectronics International N.V., Geneva (CH)
Filed by STMicroelectronics International N.V., Geneva (CH)
Filed on Feb. 13, 2023, as Appl. No. 18/168,496.
Claims priority of provisional application 63/313,137, filed on Feb. 23, 2022.
Prior Publication US 2023/0266387 A1, Aug. 24, 2023
Int. Cl. G01R 31/317 (2006.01); G01R 31/28 (2006.01); H03M 9/00 (2006.01)
CPC G01R 31/31716 (2013.01) [G01R 31/2851 (2013.01); G01R 31/31725 (2013.01); H03M 9/00 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
dividing a first clock signal having a first frequency to obtain a second clock signal having a second frequency lower than the first frequency;
providing first test data in a series of words to a serializer in accordance with the second clock signal;
generating, at the serializer, a single bit data stream by serializing the test data in accordance with the first clock signal;
generating a plurality of phase signals offset from each other in phase and each having the second frequency; and
generating second test data by sampling the single bit data stream in accordance with each of the plurality of phase signals.