US 12,449,473 B2
Virtualizing hardware processing resources in a processor
Jerome F. Duluk, Jr., Palo Alto, CA (US); Gentaro Hirota, San Jose, CA (US); Ronny Krashinsky, Portola Valley, CA (US); Greg Palmer, Cedar Park, TX (US); Jeff Tuckey, Saratoga, CA (US); Kaushik Nadadhur, Bangalore (IN); Philip Browning Johnson, San Jose, CA (US); and Praveen Joginipally, San Jose, CA (US)
Assigned to NVIDIA Corporation, Santa Clara, CA (US)
Filed by NVIDIA Corporation, Santa Clara, CA (US)
Filed on Mar. 10, 2022, as Appl. No. 17/691,759.
Prior Publication US 2023/0288471 A1, Sep. 14, 2023
Int. Cl. G01R 31/28 (2006.01); G06F 9/46 (2006.01); G06F 9/48 (2006.01); G06F 9/50 (2006.01); G06F 11/07 (2006.01)
CPC G01R 31/2884 (2013.01) [G01R 31/2839 (2013.01); G01R 31/2889 (2013.01); G01R 31/2896 (2013.01); G06F 9/46 (2013.01); G06F 9/48 (2013.01); G06F 9/50 (2013.01); G06F 11/07 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A process for testing integrated circuits comprising:
determining whether hardware processors of an integrated circuit are defective;
based on the determining, modifying the integrated circuit to selectively make hardware processors of the integrated circuit inaccessible; and
based on the determining and the modifying, programming the integrated circuit to designate non-defective hardware processors with virtual identifiers, including classifying, based on the determining, the integrated circuit in accordance with a Skyline representing a population of integrated circuits to be included in a product designator, wherein the Skyline includes (a) a declared quantity of virtual processing clusters, and (b) a declared quantity of processors for each declared virtual processing cluster, wherein different virtual processing clusters declared for the same processor, processing chip or other processing arrangement may have the same or different declared quantities of processors, wherein the Skyline is a representation declaring processing capabilities of the integrated circuit.