US 12,449,472 B2
Circuit and method for testing a circuit
Alessio Ciarcia, Munich (DE)
Assigned to Infineon Technologies AG, Neubiberg (DE)
Filed by Infineon Technologies AG, Neubiberg (DE)
Filed on Sep. 27, 2022, as Appl. No. 17/953,347.
Prior Publication US 2024/0103066 A1, Mar. 28, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G01R 31/28 (2006.01)
CPC G01R 31/2851 (2013.01) 18 Claims
OG exemplary drawing
 
1. A circuit, comprising:
a plurality of scan flip-flops including a sequence of test flip-flops, each test flip-flop having a D input, a test enable input, a test input and a Q data output,
wherein the circuit comprises, for each test flip-flop of at least a subset of the test flip-flops of the sequence, at the test flip-flop's test input a respective test input circuit having a mode control input, a shift data input, and a capture data input, the test input circuit comprises a combination of logic gates configured to,
when supplied with a mode control signal having a first value indicating a shift mode, pass from the shift data input to the test input of a respective test flip-flop the Q data output of a test flip-flop preceding the respective test flip-flop in the sequence such that the test input of the respective test flip-flop is supplied with a data content of the test flip-flop preceding the respective test flip-flop in the sequence so as to provide a test pattern to the subset of the test flip-flops of the sequence, and
when supplied with the mode control signal having a second value indicating a capture mode, pass from the capture data input to the test input of the respective test flip-flop an output of a part of the circuit to be observed such that the test input of the respective test flip-flop is supplied with a value provided by the part of the circuit so as to capture a test result to the subset of the test flip-flops of the sequence.