US 12,449,391 B2
Cell signal measurement electrode plate and information processing device provided with same
Fumitoshi Yasuo, Sakai (JP); Kenichi Kitoh, Sakai (JP); Tomoko Teranishi, Sakai (JP); and Chihiro Tachino, Sakai (JP)
Assigned to SHARP KABUSHIKI KAISHA, Sakai (JP)
Appl. No. 17/928,586
Filed by SHARP KABUSHIKI KAISHA, Sakai (JP)
PCT Filed Apr. 21, 2021, PCT No. PCT/JP2021/016123
§ 371(c)(1), (2) Date Nov. 29, 2022,
PCT Pub. No. WO2021/246070, PCT Pub. Date Dec. 9, 2021.
Claims priority of application No. 2020-097860 (JP), filed on Jun. 4, 2020.
Prior Publication US 2023/0243774 A1, Aug. 3, 2023
Int. Cl. G01N 27/414 (2006.01); G01N 27/27 (2006.01); G01N 33/483 (2006.01)
CPC G01N 27/27 (2013.01) [G01N 27/4148 (2013.01); G01N 33/4836 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A cell signal measurement electrode plate comprising:
a substrate;
a plurality of first selection lines provided on the substrate and extending in a column direction;
a plurality of second selection lines provided on the substrate and extending in a row direction;
a plurality of selection circuits and a plurality of electrodes, the plurality of selection circuits and the plurality of electrodes being configured to read a cell signal emitted from a cell, being provided on the substrate, and being arranged in a matrix shape in a portion where the plurality of first selection lines and the plurality of second selection lines intersect each other; and
a plurality of common wiring lines configured to read the cell signal, arranged in parallel with any one of the plurality of second selection lines and the plurality of first selection lines, and each connected via a selection circuit of the plurality of selection circuits to one row or one column of the plurality of electrodes arranged in the matrix shape,
wherein each of the plurality of selection circuits includes one or more unit selection circuits, and
the one or more unit selection circuits each include
a first transistor including a gate terminal connected to a first selection line of the plurality of first selection lines, and a source terminal connected to a second selection line of the plurality of second selection lines,
a second transistor including a gate terminal connected to a drain terminal of the first transistor, a source terminal connected to an electrode of the plurality of electrodes, and a drain terminal connected to a common wiring line of the plurality of common wiring lines, and
a capacitance element including one capacitance electrode connected to the drain terminal of the first transistor and another capacitance electrode connected to a wiring line configured to fix a constant potential.