US 12,449,377 B2
Method of inspecting semiconductor device
Daehyun Jung, Suwon-si (KR); Yujeong Sin, Suwon-si (KR); and Sunggon Jung, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Aug. 1, 2023, as Appl. No. 18/228,807.
Claims priority of application No. 10-2023-0002781 (KR), filed on Jan. 9, 2023.
Prior Publication US 2024/0230554 A1, Jul. 11, 2024
Int. Cl. G01N 21/95 (2006.01); G01N 21/88 (2006.01); G01N 21/956 (2006.01)
CPC G01N 21/9501 (2013.01) [G01N 21/8851 (2013.01); G01N 21/956 (2013.01); G01N 2021/8858 (2013.01); G01N 2021/8864 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of inspecting a semiconductor device, the method comprising:
scanning a plurality of first circuit pattern layers of the semiconductor device, and generating a plurality of first images respectively corresponding the plurality of first circuit pattern layers of the semiconductor device;
overlapping the plurality of first images with each other and counting a plurality of first defects in the overlapped first images;
setting main inspection areas with priority orders by using position coordinates of the counted first defects; and
storing the main inspection areas with the position coordinates of the counted first defects.