US 12,447,345 B2
Digitally adjustable phrenic nerve stimulator system
Alexey Revinski, Evanston, IL (US); Kirby D. Gong, Evanston, IL (US); Emma S. Cripe, Evanston, IL (US); Michelle Wang, Evanston, IL (US); Matthew R. Glucksberg, Evanston, IL (US); Debra E. Weese-Mayer, Chicago, IL (US); and Anthony Chin, Chicago, IL (US)
Assigned to NORTHWESTERN UNIVERSITY, Evanston, IL (US); and ANN AND ROBERT H. LURIE CHILDREN'S HOSPITAL OF CHICAGO, Chicago, IL (US)
Filed by NORTHWESTERN UNIVERSITY, Evanston, IL (US); and ANN AND ROBERT H. LURIE CHILDREN'S HOSPITAL OF CHICAGO, Chicago, IL (US)
Filed on Jan. 3, 2023, as Appl. No. 18/092,741.
Application 18/092,741 is a continuation of application No. 16/652,737, granted, now 11,633,599, previously published as PCT/US2018/055226, filed on Oct. 10, 2018.
Claims priority of provisional application 62/570,164, filed on Oct. 10, 2017.
Prior Publication US 2023/0158303 A1, May 25, 2023
Int. Cl. A61N 1/36 (2006.01); A61N 1/372 (2006.01); A61N 1/378 (2006.01)
CPC A61N 1/3611 (2013.01) [A61N 1/36034 (2017.08); A61N 1/36125 (2013.01); A61N 1/37235 (2013.01); A61N 1/3787 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A system for electrical ventilation stimulation of a patient, comprising:
an implantable nerve stimulator including:
a battery,
a central processing unit,
a plurality of hardware peripherals including a first timer, a second timer, a third timer, a digital-to-analog converter, and a direct memory access controller,
a near field communication memory tag including an adjustable setting, and
a stimulation circuit electrically coupled to the battery, wherein an output of the stimulation circuit stimulates a phrenic nerve and is controlled by the central processing unit based on the adjustable setting and the plurality of hardware peripherals; and
an external digital programming device having near field communication transmission and a digital interface, wherein the external digital programming device is configured to change the adjustable setting of the implantable nerve stimulator; and
wherein the first timer is used to control pulse timing, the second timer is used to control pulse polarity, the third timer is used to trigger digital-to-analog conversions, the digital-to-analog converter is used to control pulse magnitude, and the direct memory access controller is used to update peripheral memory registers.