US RE50,174 E1
Structure and process to tuck fin tips self-aligned to gates
Bruce B. Doris, Slingerlands, NY (US); Hong He, Schenectady, NY (US); Sivananda K. Kanakasabapathy, Niskayuna, NY (US); Gauri Karve, Cohoes, NY (US); Fee Li Lie, Albany, NY (US); Derrick Liu, Albany, NY (US); Soon-Cheon Seo, Glenmont, NY (US); and Stuart A. Sieg, Albany, NY (US)
Assigned to Tessera LLC, San Jose, CA (US)
Filed by Tessera LLC, San Jose, CA (US)
Filed on Mar. 31, 2022, as Appl. No. 17/710,394.
Application 17/710,394 is a reissue of application No. 14/719,829, filed on May 22, 2015, granted, now 9,876,074, issued on Jan. 23, 2018.
Int. Cl. H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/0649 (2013.01) [H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 29/66545 (2013.01)] 23 Claims
OG exemplary drawing
 
1. A semiconductor structure comprising:
a semiconductor fin portion having an end wall and extending upwards from a substrate;
a gate structure straddling a portion of said semiconductor fin portion;
a first set of gate spacers located on opposing sidewall surfaces of said gate structure; and
a second set of gate spacers located on outer sidewalls of said first gate spacers, wherein one gate spacer of said second set of gate spacers has an inner sidewall surface having an upper portion directly contacting said outer sidewall of one of said gate spacers of said first set of gate spacers and a lower portion directly contacting and covering an entirety of a sidewall of said end wall of said semiconductor fin portion [ , wherein:
another gate spacer of said second set of gate spacers straddles over a topmost surface of a portion of said semiconductor fin portion] .