CPC H10K 59/121 (2023.02) [G09G 3/3233 (2013.01); H10K 59/131 (2023.02); H10K 59/353 (2023.02); G09G 2300/0408 (2013.01); G09G 2300/0465 (2013.01); G09G 2300/0804 (2013.01); H10K 59/65 (2023.02)] | 20 Claims |
1. A display panel comprising a first display area and a second display area, the display panel further comprising:
a plurality of pixel blocks comprising a plurality of sub-pixels, each of the pixel blocks comprising a sub-pixels of the plurality of sub-pixels, the plurality of sub-pixels comprising a plurality of first sub-pixels located in the first display area and a plurality of second sub-pixels located in the second display area; and
a plurality of circuit blocks located in the second display area, each of the circuit blocks comprising b pixel circuits, the b pixel circuits comprising first circuits and second circuits, at least part of the first circuits being configured to drive the first sub-pixels, and the second circuits being configured to drive the second sub-pixels,
wherein both a and b are positive integers greater than 0, and a is less than b, in the second display area, an orthographic projection of the circuit block in a thickness direction of the display panel is located within an orthographic projection of the pixel block in the thickness direction.
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