	US 12,120,876 B2
	Semiconductor devices and data storage systems including the same
Seokcheon Baek, Hwaseong-si (KR); Miram Kwon, Suwon-si (KR); Seongjun Seo, Hwaseong-si (KR); and Younghwan Son, Hwaseong-si (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Feb. 24, 2022, as Appl. No. 17/679,268.
Claims priority of application No. 10-2021-0071950 (KR), filed on Jun. 3, 2021.
Prior Publication US 2022/0392916 A1, Dec. 8, 2022
Int. Cl. H10B 43/27 (2023.01); H01L 27/06 (2006.01); H10B 43/40 (2023.01)

CPC H10B 43/27 (2023.02) [H01L 27/0688 (2013.01); H10B 43/40 (2023.02)]

18 Claims

1. A semiconductor device, comprising:

a first semiconductor structure including a first substrate, circuit elements on the first substrate, and lower interconnection lines; and

a second semiconductor structure on the first semiconductor structure,

wherein the second semiconductor structure includes

a second substrate having a first region and a second region,

gate electrodes stacked on the second substrate to be spaced apart from each other in a first direction, the gate electrodes at least partially defining first and second stack structures,

interlayer insulating layers alternately stacked with the gate electrodes,

channel structures penetrating through the first and second stack structures, the channel structures extending in the first direction, the channel structures respectively including a channel layer, the channel structures being in the first region,

separation regions penetrating through the first and second stack structures and extending in a second direction,

first and second contact plugs each penetrating through the first and second stack structures and extending into the first semiconductor structure in the first direction, the first and second contact plugs being in the second region, and

contact insulating layers in contact with portions of the gate electrodes and surrounding each of the first and second contact plugs, the contact insulating layers being in the second region,

wherein the first stack structure has, in the second region,

first pad areas in which the gate electrodes extend further than upper gate electrodes, respectively, in the second direction to be connected to the first contact plugs, respectively, and

first dummy areas located on at least one side of each of the first pad areas and spaced apart from the first contact plugs,

wherein the second stack structure has, in the second region,

second pad areas in which the gate electrodes extend further than upper gate electrodes, respectively, in the second direction and connected to the second contact plugs, respectively, and

second dummy areas located on at least one side of each of the second pad areas and spaced apart from the second contact plugs, and

wherein the first pad areas overlap the second dummy areas in the first direction, and the second pad areas overlap the first dummy areas in the first direction.