US 12,120,870 B2
Semiconductor device and method for manufacturing semiconductor device
Kohei Nakagami, Yokkaichi Mie (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by KIOXIA CORPORATION, Tokyo (JP)
Filed on Sep. 3, 2021, as Appl. No. 17/466,213.
Claims priority of application No. 2020-207657 (JP), filed on Dec. 15, 2020.
Prior Publication US 2022/0189979 A1, Jun. 16, 2022
Int. Cl. H10B 41/41 (2023.01); H10B 41/27 (2023.01); H10B 43/27 (2023.01); H10B 43/40 (2023.01)
CPC H10B 41/41 (2023.02) [H10B 43/40 (2023.02); H10B 41/27 (2023.02); H10B 43/27 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a first region including a memory cell; and
a second region including a peripheral circuit, wherein
the second region includes:
a diffusion region at a surface of a semiconductor layer,
a gate insulating film on a surface of the diffusion region,
a gate electrode on the gate insulating film,
an element isolation region embedded in the semiconductor layer and surrounding the diffusion region,
a gate spacer insulator on the surface of the diffusion region, the element isolation region, and a sidewall surface of the gate electrode, the gate spacer insulator surrounding the gate electrode, and
the element isolation region having an upper surface that includes:
a first portion recessed to a level lower than the surface of the diffusion region, and
a second portion between the diffusion region and the first portion and including a protrusion protruding to a level greater than the level of the first portion.