CPC H04W 72/21 (2023.01) [H04L 5/0037 (2013.01); H04L 5/0042 (2013.01); H04L 5/0044 (2013.01); H04L 5/0053 (2013.01); H04L 5/0082 (2013.01); H04W 72/23 (2023.01); H04L 5/001 (2013.01); H04L 5/0094 (2013.01); H04W 16/14 (2013.01)] | 20 Claims |
1. An apparatus, comprising:
a processor configured to cause a base station (BS) to:
transmit a first downlink control information (DCI) message to a first UE scheduling a first plurality of uplink transmissions to the first UE, wherein the uplink transmissions of the first plurality of uplink transmissions are scheduled to be contiguous and non-overlapping in time, the first DCI message including:
bits to carry respective configurations including respective new data indicators and respective redundancy versions for respective uplink transmissions of the first plurality of uplink transmissions; and
an indication of an offset from the first DCI to a first uplink transmissions of the first plurality of uplink transmissions.
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