US 12,120,455 B2
Signal processing device, and image display device comprising same
Yongjae Choi, Seoul (KR); Dongsoo Park, Seoul (KR); Yonghyun Kim, Seoul (KR); and Wonseok Seo, Seoul (KR)
Assigned to LG ELECTRONICS INC., Seoul (KR)
Appl. No. 17/909,147
Filed by LG ELECTRONICS INC., Seoul (KR)
PCT Filed Mar. 2, 2020, PCT No. PCT/KR2020/002973
§ 371(c)(1), (2) Date Sep. 2, 2022,
PCT Pub. No. WO2021/177479, PCT Pub. Date Sep. 10, 2021.
Prior Publication US 2023/0095927 A1, Mar. 30, 2023
Int. Cl. H04N 7/10 (2006.01); H04N 5/21 (2006.01); H04N 5/52 (2006.01); H04N 7/035 (2006.01); H04N 21/426 (2011.01); H04N 21/43 (2011.01)
CPC H04N 7/102 (2013.01) [H04N 5/21 (2013.01); H04N 5/52 (2013.01); H04N 7/0352 (2013.01); H04N 21/42607 (2013.01); H04N 21/4305 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A signal processing device comprising:
an equalizer configured to receive an input signal through a channel and equalize the received input signal; and
a control circuit configured to determine an equalizer control code in response to a first signal output from the equalizer and output the determined equalizer control code to the equalizer,
wherein the equalizer equalizes the received input signal based on the equalizer control code, and
wherein in response to the first signal comprising a clock pattern signal including a first pattern signal and a second pattern signal, the control circuit applies an offset voltage to the first pattern signal and measures the magnitude of the clock pattern signal based on a difference value between the second pattern signal and the first pattern signal to which the offset voltage is applied.