US 12,120,349 B2
Encoder, decoder, encoding method, and decoding method
Ryuichi Kanoh, Osaka (JP); Tadamasa Toma, Osaka (JP); Kiyofumi Abe, Osaka (JP); Takahiro Nishi, Nara (JP); Masato Ohkawa, Toyama (JP); and Hideo Saitou, Ishikawa (JP)
Assigned to PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA, Torrance, CA (US)
Filed by Panasonic Intellectual Property Corporation of America, Torrance, CA (US)
Filed on Aug. 17, 2022, as Appl. No. 17/889,580.
Application 17/889,580 is a continuation of application No. 16/840,906, filed on Apr. 6, 2020, granted, now 11,457,240.
Application 16/840,906 is a continuation of application No. PCT/JP2018/035903, filed on Sep. 27, 2018.
Claims priority of provisional application 62/570,784, filed on Oct. 11, 2017.
Claims priority of provisional application 62/569,200, filed on Oct. 6, 2017.
Prior Publication US 2022/0394296 A1, Dec. 8, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H04N 11/02 (2006.01); H04N 19/124 (2014.01); H04N 19/176 (2014.01); H04N 19/44 (2014.01); H04N 19/60 (2014.01)
CPC H04N 19/60 (2014.11) [H04N 19/124 (2014.11); H04N 19/176 (2014.11); H04N 19/45 (2014.11)] 2 Claims
OG exemplary drawing
 
1. An encoder comprising:
circuitry; and
memory,
wherein the circuitry, using the memory:
determines a first group of candidates and transforms a current block using a transform basis which is one of the candidates included in the first group of candidates determined, when the current block has a size of 16 or less; and
determines one second candidate outside of the first group of candidates and transforms the current block using a transform basis which is the second candidate determined, when the current block has a size larger than 16.