US 12,120,331 B2
System and method for compressing image based on flash in-memory computing array
Jinfeng Kang, Beijing (CN); Yachen Xiang, Beijing (CN); Peng Huang, Beijing (CN); Xiaoyan Liu, Beijing (CN); and Runze Han, Beijing (CN)
Assigned to Peking University, Beijing (CN)
Appl. No. 17/634,442
Filed by Peking University, Beijing (CN)
PCT Filed Dec. 31, 2019, PCT No. PCT/CN2019/130472
§ 371(c)(1), (2) Date Feb. 10, 2022,
PCT Pub. No. WO2021/027238, PCT Pub. Date Feb. 18, 2021.
Claims priority of application No. 201910738965.3 (CN), filed on Aug. 12, 2019.
Prior Publication US 2022/0321900 A1, Oct. 6, 2022
Int. Cl. H04N 19/423 (2014.01); H04N 19/124 (2014.01); H04N 19/127 (2014.01)
CPC H04N 19/423 (2014.11) [H04N 19/124 (2014.11); H04N 19/127 (2014.11)] 8 Claims
OG exemplary drawing
 
1. A system for compressing an image based on a FLASH in-memory computing array, comprising: a convolutional neural network for encoding based on the FLASH in-memory computing array, a convolutional neural network for decoding based on the FLASH in-memory computing array, and a quantization module;
wherein the convolutional neural network for encoding based on the FLASH in-memory computing array is configured to encode an original image to obtain a feature image;
wherein the quantization module is configured to quantize the feature image to obtain a quantized image;
wherein the convolutional neural network for decoding based on the FLASH in-memory computing array is configured to decode the quantized image to obtain a compressed image;
wherein each layer in the convolutional neural network for encoding and each layer in the convolutional neural network for decoding comprises: an in-memory computing array based on FLASH, wherein the in-memory computing array based on FLASH comprises: a plurality of FLASH cells, a plurality of word lines, a plurality of source lines, a plurality of bit lines, and a plurality of subtractors;
wherein the in-memory computing array is composed of the plurality of FLASH cells, gate electrodes of the FLASH cells in each column are connected to the same word line, source electrodes of the FLASH cells in each column are connected to the same source line, drain electrodes of the FLASH cells in each row are connected to the same bit line, and a positive terminal and a negative terminal of each subtractor are respectively connected to two adjacent bit lines.