US 12,119,822 B2
Signal generation circuit having minimum delay, semiconductor apparatus using the same, and signal generation method
Young Ouk Kim, Icheon-si Gyeonggi-do (KR); and Gyu Tae Park, Icheon-si Gyeonggi-do (KR)
Assigned to SK hynix Inc., Icheon-si Gyeonggi-do (KR)
Filed by SK hynix Inc., Icheon-si Gyeonggi-do (KR)
Filed on Aug. 16, 2023, as Appl. No. 18/450,749.
Application 18/450,749 is a division of application No. 17/725,904, filed on Apr. 21, 2022, granted, now 11,777,474.
Application 17/725,904 is a continuation of application No. 17/170,417, filed on Feb. 8, 2021, granted, now 11,349,457, issued on May 31, 2022.
Claims priority of application No. 10-2020-0121949 (KR), filed on Sep. 22, 2020.
Prior Publication US 2023/0396239 A1, Dec. 7, 2023
Int. Cl. H03K 3/017 (2006.01); H03K 5/00 (2006.01); H03K 5/01 (2006.01); H03L 7/081 (2006.01)
CPC H03K 3/017 (2013.01) [H03K 5/01 (2013.01); H03L 7/0812 (2013.01); H03K 2005/00019 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A semiconductor apparatus comprising:
a clock divider configured to generate a first divided clock signal and a second divided clock signal by dividing an input clock signal;
a first duty correction circuit configured to generate a first reference clock signal and a second reference clock signal by delaying the first and second divided clock signals, compare the phases of the first and second reference clock signals to adjust a delay time of the second divided clock signal by a first time, and then decrease a delay time of the first divided clock signal and the delay time of the second divided clock signal by a second time; and
a delay locked loop circuit configured to compare the phases of the first reference clock signal and a feedback clock signal and generate at least one output clock signal by delaying the first and second reference clock signals, and generate the feedback clock signal by delaying the at least one output clock signal.