US 12,119,816 B2
Semiconductor device and semiconductor device control method
Keisuke Kiyomizu, Yokohama (JP)
Assigned to LAPIS Technology Co., Ltd., Yokohama (JP)
Filed by LAPIS Technology Co., Ltd., Yokohama (JP)
Filed on Sep. 26, 2022, as Appl. No. 17/953,023.
Claims priority of application No. 2021-160661 (JP), filed on Sep. 30, 2021.
Prior Publication US 2023/0109445 A1, Apr. 6, 2023
Int. Cl. H03K 17/687 (2006.01); H03K 3/037 (2006.01)
CPC H03K 17/6872 (2013.01) [H03K 3/037 (2013.01)] 6 Claims
OG exemplary drawing
 
1. A semiconductor device that operates at a first power source voltage and at a second power source voltage higher than the first power source voltage and that comprises:
a first first-conductivity-type transistor supplied with the first power source voltage and controlled by an output signal of a first input inverter that inverts an input signal;
a second first-conductivity-type transistor supplied with the first power source voltage and controlled by an output signal of a second input inverter that inverts the output signal of the first input inverter;
a first second-conductivity-type transistor supplied with the second power source voltage;
a second second-conductivity-type transistor supplied with the second power source voltage; and
a third first-conductivity-type transistor and a fourth first-conductivity-type transistor that are connected in parallel either between the first first-conductivity-type transistor and the first second-conductivity-type transistor or between the second first-conductivity-type transistor and the second second-conductivity-type transistor, and that are configured to isolate either a first node connected to the first first-conductivity-type transistor or a second node connected to the second first-conductivity-type transistor from the second power source voltage in accordance with the first power source voltage;
wherein:
the output signal of the first input inverter is supplied to a gate of the third first-conductivity-type transistor; and
the output signal of the second input inverter is supplied to a gate of the fourth first-conductivity-type transistor.