| CPC H03F 3/211 (2013.01) [G09G 3/3275 (2013.01); G09G 2310/0291 (2013.01); G09G 2320/0252 (2013.01); G09G 2330/021 (2013.01); H03F 2200/366 (2013.01); H03F 2200/87 (2013.01)] | 21 Claims |
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1. An amplifier circuit comprising:
a first stage including a first input terminal and a second input terminal, the first stage configured to supply a voltage;
a second stage connected to the first stage and configured to amplify the voltage supplied from the first stage, the second stage including a pull-up node and a pull-down node;
a third stage including an output terminal, a tenth PMOS transistor having a gate electrode connected to the pull-up node of the second stage, and a tenth NMOS transistor having a gate electrode connected to the pull-down node of the second stage, the third stage configured to perform a pull-up driving of the amplified voltage supplied from the second stage or a pull-down driving of the amplified voltage supplied from the second stage;
a first boosting circuit including an eleventh PMOS transistor having a gate electrode connected to the pull-up node included the second stage and the gate electrode of the tenth PMOS transistor included in the third stage, the first boosting circuit configured to increase a current in the first stage while the eleventh PMOS transistor is turned on; and
a second boosting circuit including an eleventh NMOS transistor having a gate electrode connected to the pull-down node included the second stage and the gate electrode of the tenth NMOS transistor included in the third stage, the second boosting circuit configured to increase the current in the first stage while the eleventh NMOS transistor is turned on.
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