US 12,119,397 B2
Semiconductor IC device including passivation layer for inactivating a dopant in a p-type semiconductor layer and method of manufacturing the same
Sunkyu Hwang, Seoul (KR); Jongseob Kim, Seoul (KR); Joonyong Kim, Seoul (KR); Younghwan Park, Seongnam-si (KR); Junhyuk Park, Pohang-si (KR); Jaejoon Oh, Seongnam-si (KR); and Injun Hwang, Yongin-si (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Sep. 2, 2021, as Appl. No. 17/465,212.
Claims priority of application No. 10-2021-0061645 (KR), filed on May 12, 2021.
Prior Publication US 2022/0367698 A1, Nov. 17, 2022
Int. Cl. H01L 29/00 (2006.01); H01L 29/20 (2006.01); H01L 29/66 (2006.01); H01L 29/778 (2006.01)
CPC H01L 29/7786 (2013.01) [H01L 29/2003 (2013.01); H01L 29/66431 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A semiconductor integrated circuit device comprising:
a channel layer;
a barrier layer on the channel layer and configured to induce a 2-dimensional electron gas (2DEG) in the channel layer;
a first p-type semiconductor layer and a second p-type semiconductor layer spaced apart from each other on the barrier layer; and
a passivation layer on the first p-type semiconductor layer and the second p-type semiconductor layer,
wherein the passivation layer is configured to partially inactivate at least one of a dopant of the first p-type semiconductor layer or a dopant of the second p-type semiconductor layer.