US 12,119,396 B2
Semiconductor device
Yasunobu Saito, Ishikawa (JP)
Assigned to Kabushiki Kaisha Toshiba, Tokyo (JP); and Toshiba Electronic Devices & Storage Corporation, Tokyo (JP)
Filed by KABUSHIKI KAISHA TOSHIBA, Tokyo (JP); and TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION, Tokyo (JP)
Filed on Oct. 5, 2021, as Appl. No. 17/494,639.
Application 17/494,639 is a division of application No. 16/287,394, filed on Feb. 27, 2019, abandoned.
Claims priority of application No. 2018-173396 (JP), filed on Sep. 18, 2018.
Prior Publication US 2022/0029006 A1, Jan. 27, 2022
Int. Cl. H01L 29/778 (2006.01); H01L 29/423 (2006.01)
CPC H01L 29/7783 (2013.01) [H01L 29/4236 (2013.01); H01L 29/7786 (2013.01); H01L 29/7787 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a first nitride semiconductor layer on a substrate;
a source electrode on the first nitride semiconductor layer;
a drain electrode on the first nitride semiconductor layer;
a gate electrode between the source electrode and the drain electrode;
a second nitride semiconductor region between the first nitride semiconductor layer and the drain electrode and being a material having a larger bandgap than the first nitride semiconductor layer;
a third nitride semiconductor region directly on the first nitride semiconductor layer, a lateral position of the third nitride semiconductor region being between a lateral position of a drain-side edge of the gate electrode and a lateral position of a gate-side edge of the drain electrode, a lateral surface of third nitride semiconductor region directly contacting the second nitride semiconductor region, the third nitride semiconductor region being a material having a bandgap larger than the first nitride semiconductor layer and less than or equal to the material of the second nitride semiconductor region; and
a fourth nitride semiconductor region between the first nitride semiconductor layer and the source electrode and being a material having a larger bandgap than the first nitride semiconductor layer and the material of the third nitride semiconductor region, wherein
the gate electrode is between the third nitride semiconductor region and the fourth nitride semiconductor region in a direction substantially parallel to a plane of the substrate.