US 12,119,394 B2
Method of manufacturing a semiconductor device and a semiconductor device
Shahaji B. More, Hsinchu (TW); Chien Lin, Hsinchu (TW); Cheng-Han Lee, New Taipei (TW); Shih-Chieh Chang, Taipei (TW); and Shu Kuan, Keelung (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Jun. 17, 2022, as Appl. No. 17/843,601.
Application 17/843,601 is a division of application No. 16/902,170, filed on Jun. 15, 2020, granted, now 11,367,784, issued on Jun. 21, 2022.
Prior Publication US 2022/0320321 A1, Oct. 6, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/66 (2006.01); H01L 21/306 (2006.01); H01L 21/8234 (2006.01); H01L 29/10 (2006.01); H01L 29/161 (2006.01); H01L 29/423 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/66818 (2013.01) [H01L 21/30604 (2013.01); H01L 21/823431 (2013.01); H01L 29/1054 (2013.01); H01L 29/161 (2013.01); H01L 29/42392 (2013.01); H01L 29/66553 (2013.01); H01L 29/6656 (2013.01); H01L 29/785 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor device, comprising:
forming a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked;
forming a sacrificial gate structure over the fin structure;
etching a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming a source/drain space;
laterally etching the second semiconductor layers through the source/drain space;
forming an inner spacer made of a dielectric material on an end of each of the etched second semiconductor layers; and
forming a source/drain epitaxial layer in the source/drain space to cover the inner spacer,
wherein at least one of the first semiconductor layers has a composition which changes along a stacked direction of the first semiconductor layers and second semiconductor layers.