US 12,119,387 B2
Low resistance approaches for fabricating contacts and the resulting structures
Gilbert Dewey, Beaverton, OR (US); Nazila Haratipour, Hillsboro, OR (US); Siddharth Chouksey, Portland, OR (US); Jack T. Kavalieros, Portland, OR (US); Jitendra Kumar Jha, Hillsboro, OR (US); Matthew V. Metz, Portland, OR (US); Mengcheng Lu, Portland, OR (US); Anand S. Murthy, Portland, OR (US); Koustav Ganguly, Beaverton, OR (US); Ryan Keech, Portland, OR (US); Glenn A. Glass, Portland, OR (US); and Arnab Sen Gupta, Hillsboro, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 25, 2020, as Appl. No. 17/033,471.
Prior Publication US 2022/0102521 A1, Mar. 31, 2022
Int. Cl. H01L 29/45 (2006.01); H01L 21/285 (2006.01); H01L 21/768 (2006.01); H01L 23/485 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/40 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/775 (2006.01); H01L 29/78 (2006.01); H01L 29/786 (2006.01)
CPC H01L 29/45 (2013.01) [H01L 21/28518 (2013.01); H01L 29/0673 (2013.01); H01L 29/0847 (2013.01); H01L 29/41733 (2013.01); H01L 29/42392 (2013.01); H01L 29/66545 (2013.01); H01L 29/66742 (2013.01); H01L 29/66795 (2013.01); H01L 29/7851 (2013.01); H01L 29/78618 (2013.01); H01L 29/78696 (2013.01)] 10 Claims
OG exemplary drawing
 
1. An integrated circuit structure, comprising:
a semiconductor structure above a substrate;
a gate electrode over the semiconductor structure, the gate electrode defining a channel region in the semiconductor structure;
a first semiconductor source or drain structure at a first end of the channel region at a first side of the gate electrode;
a second semiconductor source or drain structure at a second end of the channel region at a second side of the gate electrode, the second end opposite the first end; and
a source or drain contact directly on and in direct physical contact with the first or second semiconductor source or drain structure, the source or drain contact comprising a barrier layer and an inner conductive structure, wherein the barrier layer is a metal nitride barrier layer or a metal carbide barrier layer.