| CPC H01L 27/1225 (2013.01) [H01L 27/1255 (2013.01); H01L 29/7869 (2013.01); H10B 12/20 (2023.02)] | 5 Claims |
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1. A semiconductor device comprising:
a cell array comprising a first memory cell and a second memory cell;
a first driver circuit configured to supply a selection signal; and
a second driver circuit configured to write or read out data,
wherein the first memory cell comprises a first transistor and a first capacitor,
wherein the second memory cell comprises a second transistor and a second capacitor,
wherein one of a source and a drain of the first transistor is electrically connected to the first capacitor,
wherein one of a source and a drain of the second transistor is electrically connected to the second capacitor,
wherein each of the first transistor and the second transistor includes a first oxide semiconductor layer and a second oxide semiconductor layer over the first oxide semiconductor layer,
wherein the first transistor includes at least a first channel formation region formed in the second oxide semiconductor layer, a third oxide semiconductor layer over the first channel formation region, a first gate electrode over the third oxide semiconductor layer, and a second gate electrode under the first channel formation region, and
wherein the second transistor includes at least a second channel formation region formed in the second oxide semiconductor layer, a fourth oxide semiconductor layer over the second channel formation region, a third gate electrode over the fourth oxide semiconductor layer, and a fourth gate electrode under the second channel formation region.
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