	US 12,119,336 B2
	Fusion memory device and method of fabricating the same
Hyunmog Park, Seoul (KR); Daehyun Kim, Suwon-si (KR); Jinmin Kim, Seoul (KR); Hei Seung Kim, Suwon-si (KR); Hyunsik Park, Seoul (KR); and Sangkil Lee, Seongnam-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Aug. 9, 2022, as Appl. No. 17/883,682.
Application 17/883,682 is a continuation of application No. 16/459,725, filed on Jul. 2, 2019, granted, now 11,462,528.
Claims priority of application No. 10-2018-0167111 (KR), filed on Dec. 21, 2018.
Prior Publication US 2022/0384410 A1, Dec. 1, 2022
Int. Cl. H01L 25/18 (2023.01); G11C 14/00 (2006.01); G11C 16/04 (2006.01); H01L 23/48 (2006.01); H01L 23/522 (2006.01); H01L 25/00 (2006.01); H10B 41/00 (2023.01); H10B 41/27 (2023.01); H10B 43/27 (2023.01); G11C 13/00 (2006.01); H10B 41/41 (2023.01)

CPC H01L 25/18 (2013.01) [G11C 14/0018 (2013.01); G11C 16/04 (2013.01); H01L 23/481 (2013.01); H01L 23/5226 (2013.01); H01L 25/50 (2013.01); H10B 41/27 (2023.02); H10B 43/27 (2023.02); G11C 13/0004 (2013.01); H10B 41/41 (2023.02)]

20 Claims

1. A method of fabricating a fusion memory device, the method comprising:

forming a first memory cell circuit including a plurality of first memory cells on an active surface of a first substrate;

forming a non-memory circuit including a plurality of conductive lines on an active surface of a second substrate;

combining the first memory cell circuit with the non-memory circuit; and

forming a second memory cell circuit including a plurality of second memory cells on an inactive surface of the second substrate,

wherein forming the first memory cell circuit and forming the non-memory circuit are performed independently of each other, and

wherein forming the first memory cell circuit is performed at a first temperature higher than a second temperature of forming the second memory cell circuit, and

wherein forming the second memory cell circuit does not include a diffusion process.