US 12,119,335 B2
Interconnection structures for high bandwidth data transfer
Joshua M Rubin, Albany, NY (US); Steven Lorenz Wright, Tucson, AZ (US); Arvind Kumar, Chappaqua, NY (US); and Mounir Meghelli, Tarrytown, NY (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Dec. 16, 2021, as Appl. No. 17/552,754.
Prior Publication US 2023/0197705 A1, Jun. 22, 2023
Int. Cl. H01L 25/18 (2023.01)
CPC H01L 25/18 (2013.01) 21 Claims
OG exemplary drawing
 
1. A semiconductor memory module comprising:
a module substrate comprising active components and passive components, wherein the active components comprise companion physical layers, a memory controller, a SERDES, and an I/O connection,
wherein the SERDES and the I/O connection are communicatively coupled with a serial communication link, and
wherein the I/O connection is located a communication distance greater than 8 mm from the companion physical layers;
a high bandwidth semiconductor chip comprising a physical layer physically secured to the module substrate, wherein the physical layer of the high bandwidth semiconductor chip is communicatively coupled to the SERDES via a companion parallel connection, the companion physical layers, a parallel communication link, and the memory controller.