US 12,119,331 B2
Semiconductor package
Ju-Il Choi, Seongnam-si (KR); Gyuho Kang, Cheonan-si (KR); Heewon Kim, Anyang-si (KR); Sechul Park, Bucheon-si (KR); Jongho Park, Cheonan-si (KR); and Junyoung Park, Anyang-si (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Feb. 22, 2022, as Appl. No. 17/677,453.
Claims priority of application No. 10-2021-0076873 (KR), filed on Jun. 14, 2021.
Prior Publication US 2022/0399316 A1, Dec. 15, 2022
Int. Cl. H01L 23/498 (2006.01); H01L 23/00 (2006.01); H01L 23/48 (2006.01); H01L 23/538 (2006.01); H01L 25/10 (2006.01); H01L 25/065 (2023.01)
CPC H01L 25/105 (2013.01) [H01L 23/481 (2013.01); H01L 23/49816 (2013.01); H01L 23/49822 (2013.01); H01L 23/49838 (2013.01); H01L 23/5383 (2013.01); H01L 23/5386 (2013.01); H01L 24/08 (2013.01); H01L 24/32 (2013.01); H01L 23/49833 (2013.01); H01L 24/80 (2013.01); H01L 25/0657 (2013.01); H01L 2224/08237 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/80895 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/1023 (2013.01); H01L 2225/1058 (2013.01); H01L 2225/1094 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1434 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
an interposer substrate having a first surface and a second surface that are opposite to each other, the interposer substrate including a wiring layer adjacent to the first surface and a plurality of through electrodes that penetrate the interposer substrate and connect to the wiring layer, each of the plurality of through electrodes extending from the wiring layer toward the second surface;
a semiconductor chip on the first surface of the interposer substrate;
a passivation layer on the first surface of the interposer substrate, the passivation layer covering the semiconductor chip; and
a plurality of redistribution patterns in the passivation layer and connected to the semiconductor chip,
wherein the semiconductor chip has a third surface and a fourth surface that are opposite to each other, the third surface of the semiconductor chip faces the first surface of the interposer substrate, and the plurality of redistribution patterns are connected to the fourth surface of the semiconductor chip,
wherein the semiconductor chip includes:
a plurality of chip pads adjacent to the third surface;
a semiconductor substrate on the plurality of chip pads;
a plurality of chip through electrodes penetrating the semiconductor substrate and spaced apart from each other in the semiconductor substrate;
a circuit layer on the semiconductor substrate; and
a chip wiring layer on the circuit layer and adjacent to the fourth surface,
wherein the plurality of chip through electrodes are connected to the plurality of chip pads,
wherein each of the plurality of chip pads is directly connected to a corresponding one of a plurality of wiring patterns in the wiring layer of the interposer substrate, and
wherein the plurality of redistribution patterns are connected to a plurality of chip wiring patterns in the chip wiring layer.