US 12,119,329 B2
Semiconductor package and method of fabricating the same
Eunkyul Oh, Gwacheon-si (KR); Yunrae Cho, Guri-si (KR); Taeheon Kim, Anyang-si (KR); and Seunghun Han, Seoul (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Aug. 11, 2023, as Appl. No. 18/448,284.
Application 18/448,284 is a continuation of application No. 17/662,162, filed on May 5, 2022, granted, now 11,769,755.
Application 17/662,162 is a continuation of application No. 16/896,897, filed on Jun. 9, 2020, granted, now 11,335,668, issued on May 17, 2022.
Claims priority of application No. 10-2019-0136942 (KR), filed on Oct. 30, 2019.
Prior Publication US 2023/0387083 A1, Nov. 30, 2023
Int. Cl. H01L 23/00 (2006.01); H01L 21/56 (2006.01); H01L 21/66 (2006.01); H01L 21/768 (2006.01); H01L 21/78 (2006.01); H01L 23/48 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01); H01L 25/18 (2023.01)
CPC H01L 25/0657 (2013.01) [H01L 21/565 (2013.01); H01L 21/76898 (2013.01); H01L 21/78 (2013.01); H01L 22/12 (2013.01); H01L 22/32 (2013.01); H01L 23/481 (2013.01); H01L 24/14 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H01L 2224/14517 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06586 (2013.01); H01L 2225/06596 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor package comprising:
an interface chip comprising a first pad provided in an outer portion of the interface chip, a second pad provided inside the first pad, and a first through silicon via (TSV) provided between the first pad and the second pad;
at least one memory chip stacked on the interface chip, wherein the at least one memory chip comprises a third pad provided in an outer portion of the at least one memory chip, a fourth pad provided inside the third pad, and a second TSV provided between the third pad and the fourth pad; and
an adhesive layer provided between the interface chip and the at least one memory chip,
wherein a first bump is provided on the second pad on a bottom surface of the interface chip,
a second bump is provided on the second TSV on a bottom surface of the at least one memory chip,
a dummy bump is provided on the bottom surface of the at least one memory chip to be adjacent to the second bump, and
each of the first pad and the third pad comprises a groove.