US 12,119,298 B2
Semiconductor memory device
Genki Kawaguchi, Yokkaichi (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Feb. 3, 2022, as Appl. No. 17/591,713.
Claims priority of application No. 2021-106099 (JP), filed on Jun. 25, 2021.
Prior Publication US 2022/0415787 A1, Dec. 29, 2022
Int. Cl. H01L 41/27 (2013.01); H01L 23/522 (2006.01); H10B 41/27 (2023.01); H10B 43/27 (2023.01)
CPC H01L 23/5226 (2013.01) [H10B 41/27 (2023.02); H10B 43/27 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A semiconductor memory device comprising:
a substrate expanding in a first direction and a second direction and including a first area and a second area arranged in the first direction, the first direction intersecting the second direction;
a plurality of conductive layers arranged in a third direction with a distance therebetween, the third direction intersecting the first direction and the second direction, the conductive layers including a first conductive layer and each of the conductive layers including a first portion and a second portion arranged with the first portion in the second direction, the first portion extending in the first direction over the second area and the second portion including a terrace portion provided so as not to overlap an upper conductive layer of the conductive layers in the third direction;
a first insulating portion provided between the first portions of the conductive layers and the second portions of the conductive layers;
a first insulating layer arranged with the first portion of the first conductive layer in the second direction with the first insulating portion interposed therebetween; and
a first memory pillar passing through the conductive layers in the third direction in the first area, a portion of the first memory pillar intersecting the first conductive layer functioning as a first memory cell transistor.