CPC H01L 21/823487 (2013.01) [H01L 21/823412 (2013.01); H01L 21/823418 (2013.01); H01L 21/823437 (2013.01); H01L 21/823475 (2013.01); H01L 21/823885 (2013.01); H01L 23/528 (2013.01); H01L 29/0847 (2013.01); H01L 29/1037 (2013.01); H01L 29/7827 (2013.01); H01L 29/785 (2013.01); H01L 29/78642 (2013.01); H01L 29/7926 (2013.01); H10B 12/395 (2023.02); H10B 51/30 (2023.02); H10B 53/30 (2023.02); H10B 63/34 (2023.02); H10B 99/00 (2023.02); H01L 21/31111 (2013.01); H01L 21/76802 (2013.01); H01L 21/76877 (2013.01)] | 20 Claims |
1. An array of vertical transistors, comprising:
spaced pillars individually comprising a channel region of individual vertical transistors;
a horizontally-elongated conductor line directly electrically coupling together individual of the channel regions of the pillars of a plurality of the vertical transistors; and
an upper source/drain region above the individual channel regions of the pillars, a lower source/drain region below the individual channel regions of the pillars, and a conductive gate line operatively aside the individual channel regions of the pillars and that interconnects multiple of the vertical transistors.
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