US 12,119,075 B2
Efficient soft decoding of error correction code via extrinsic bit information
Avi Steiner, Kiriat Motzkin (IL); Ofir Kanter, Haifa (IL); and Yasuhiko Kurosawa, Fujisawa Kanagawa (JP)
Assigned to KIOXIA CORPORATION, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Mar. 16, 2023, as Appl. No. 18/185,198.
Prior Publication US 2024/0312552 A1, Sep. 19, 2024
Int. Cl. G06F 11/10 (2006.01); G06F 11/07 (2006.01); G06F 11/30 (2006.01); G06F 13/16 (2006.01); G06F 13/28 (2006.01); G11C 29/02 (2006.01); G11C 29/52 (2006.01); H03M 13/11 (2006.01); H03M 13/15 (2006.01)
CPC G11C 29/52 (2013.01) [G11C 29/022 (2013.01); G11C 29/024 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A computer-implemented method of soft correction in a memory device, the computer-implemented method comprising:
selecting a plurality of memory locations at a memory device, the memory locations corresponding to a first page including a first plurality of bits and a second page including a second plurality of bits;
modifying, based on the first plurality of bits and the second plurality of bits, a first voltage threshold corresponding to an estimated read voltage for the first plurality of bits;
allocating, to a voltage range bounded by the first voltage threshold, a log-likelihood ratio (LLR); and
decoding, based on the LLR corresponding to the voltage range, the first plurality of bits.