US 12,119,063 B2
Memory device and operation method thereof
Sang-Wan Nam, Hwaseong-si (KR); Hyunggon Kim, Hwaseong-si (KR); Bong-Kil Jung, Seoul (KR); Younho Hong, Seoul (KR); and Juseong Hwang, Suwon-si (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Sep. 30, 2022, as Appl. No. 17/957,532.
Claims priority of application No. 10-2021-0150932 (KR), filed on Nov. 4, 2021.
Prior Publication US 2023/0138601 A1, May 4, 2023
Int. Cl. G11C 16/08 (2006.01)
CPC G11C 16/08 (2013.01) 20 Claims
OG exemplary drawing
 
1. A memory device comprising;
a memory block connected with a plurality of wordlines;
a voltage generating circuit configured to output a first non-selection voltage through a plurality of driving lines; and
an address decoding circuit configured to connect the plurality of driving lines with unselected wordlines of the plurality of wordlines,
wherein, during a wordline setup period for the plurality of wordlines,
the plurality of driving lines include first driving lines corresponding to first unselected wordlines among the unselected wordlines and second driving lines corresponding to second unselected wordlines among the unselected wordlines,
the voltage generating circuit is further configured to float the first driving lines when the first unselected wordlines reach a first target level,
the voltage generating circuit is further configured to float the second driving lines when the second unselected wordlines reach a second target level, and
the second target level is different from the first target level.