US 12,119,049 B2
Memory controller performing data training, system-on-chip including the memory controller, and operating method of the memory controller
Daero Kim, Hwaseong-si (KR); Kyunghoi Koo, Suwon-si (KR); Sujeong Kim, Hwaseong-si (KR); Juyoung Kim, Hwaseong-si (KR); Sanghune Park, Seongnam-si (KR); Jiyeon Park, Suwon-si (KR); Jihun Oh, Hwaseong-si (KR); and Kyoungwon Lee, Uijeongbu-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Oct. 19, 2023, as Appl. No. 18/490,042.
Application 18/490,042 is a continuation of application No. 17/569,679, filed on Jan. 6, 2022, granted, now 11,830,541.
Claims priority of application No. 10-2021-0074295 (KR), filed on Jun. 8, 2021.
Prior Publication US 2024/0046982 A1, Feb. 8, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 11/4076 (2006.01); G11C 11/4096 (2006.01); G06F 13/16 (2006.01); G11C 7/10 (2006.01); G11C 7/14 (2006.01); G11C 11/4093 (2006.01)
CPC G11C 11/4096 (2013.01) [G11C 11/4076 (2013.01); G06F 13/1689 (2013.01); G11C 7/1066 (2013.01); G11C 7/1084 (2013.01); G11C 7/1093 (2013.01); G11C 7/14 (2013.01); G11C 11/4093 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system-on-chip comprising:
a memory device unit configured to operate in synchronization with an clock signal; and
a memory control unit configured to control an operation of the memory device unit,
wherein the memory control unit comprises:
a first receiver configured to compare a read reference voltage with a piece of data received through a first data line and configured to output a first piece of data;
a first duty adjuster connected to an output of the first receiver and configured to adjust a duty of the first piece of data;
a second receiver configured to compare the read reference voltage with a piece of data received through a second data line and configured to output a second piece of data;
a second duty adjuster connected to an output of the second receiver and configured to adjust a duty of the second piece of data; and
a training circuit configured to perform a training operation on pieces of data received through a plurality of data lines, to obtain a target read reference voltage for each of the pieces of data and correct a duty of each of the pieces of data based on a level of the target read reference voltage for each of the pieces of data,
wherein based on a result of the training operation, the duty of the first piece of data and the duty of the second piece of data are differently adjusted based on a level of a first target read reference voltage obtained for the first piece of data being different from a level of a second target read reference voltage obtained for the second piece of data.