US 12,118,947 B2
Scanning line drive circuit and display device provided with same
Nobuyuki Taya, Sakai (JP); Makoto Yokoyama, Sakai (JP); and Naoki Ueda, Sakai (JP)
Assigned to SHARP KABUSHIKI KAISHA, Sakai (JP)
Appl. No. 18/028,710
Filed by Sharp Kabushiki Kaisha, Sakai (JP)
PCT Filed Oct. 2, 2020, PCT No. PCT/JP2020/037542
§ 371(c)(1), (2) Date Mar. 27, 2023,
PCT Pub. No. WO2022/070404, PCT Pub. Date Apr. 7, 2022.
Prior Publication US 2023/0335061 A1, Oct. 19, 2023
Int. Cl. G09G 3/3266 (2016.01); G09G 3/3233 (2016.01); G11C 19/28 (2006.01)
CPC G09G 3/3266 (2013.01) [G09G 3/3233 (2013.01); G11C 19/287 (2013.01); G09G 2300/0819 (2013.01); G09G 2300/0852 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/08 (2013.01); G09G 2320/041 (2013.01); G09G 2320/043 (2013.01)] 7 Claims
OG exemplary drawing
 
1. A scanning line drive circuit having a configuration in which a plurality of unit circuits are connected in multiple stages,
wherein each of the unit circuits includes
a first transistor having a first conductive terminal to which a first-level voltage is applied and a second conductive terminal connected to a first node,
a second transistor having a second conductive terminal to which a second-level voltage is applied,
a third transistor having a first conductive terminal connected to the first node and a second conductive terminal connected to a first conductive terminal of the second transistor,
a fourth transistor having a first conductive terminal connected to a control terminal of the third transistor, and having a second conductive terminal and a control terminal to both of which the second-level voltage is applied, and
an output transistor having a control terminal connected to the first node and a second conductive terminal connected to an output terminal.