CPC G09G 3/32 (2013.01) [G09G 3/2092 (2013.01); G09G 2300/0408 (2013.01); G09G 2300/0426 (2013.01); G09G 2300/0452 (2013.01); G09G 2310/0267 (2013.01); G09G 2310/06 (2013.01); G09G 2320/0204 (2013.01); G09G 2320/0233 (2013.01); G09G 2330/06 (2013.01)] | 16 Claims |
1. A driving circuit for a display panel, comprising:
a driving-signal generating circuit, generating a driving signal in a frame time to drive a display element of said display panel, said driving signal including at least one first turn-on pulse width, at least one second turn-on pulse width, and at least one third turn-on pulse width, said first turn-on pulse width greater than said second turn-on pulse width and said third turn-on pulse width, said second turn-on pulse width smaller than said third turn-on pulse width;
wherein said driving-signal generating circuit generates said driving signal according to a clock signal with a plurality of clock pulses; the frequency of said clock signal is a first frequency, a second frequency, or a third frequency; said driving-signal generating circuit generates said first turn-on pulse width according to said clock signal with said first frequency, said second turn-on pulse width according to said clock signal with said second frequency, and said third turn-on pulse width according to said clock signal with said third frequency.
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