US 12,118,918 B2
Method and system for transmitting data, timing controller, and source driver chip
Jangjin Nam, Beijing (CN); Dongmyung Lee, Beijing (CN); Donghoon Baek, Beijing (CN); and Daejoon Lee, Beijing (CN)
Assigned to Beijing ESWIN Computing Technology Co., Ltd., Beijing (CN); and Hefei ESWIN Computing Technology Co., Ltd., Hefei (CN)
Filed by Beijing ESWIN Computing Technology Co., Ltd., Beijing (CN); and Hefei ESWIN Computing Technology Co., Ltd., Hefei (CN)
Filed on Dec. 28, 2022, as Appl. No. 18/147,204.
Claims priority of application No. 202210601155.5 (CN), filed on May 30, 2022.
Prior Publication US 2023/0386388 A1, Nov. 30, 2023
Int. Cl. G09G 3/20 (2006.01)
CPC G09G 3/2096 (2013.01) [G09G 2370/08 (2013.01)] 20 Claims
OG exemplary drawing
 
20. A system for transmitting data, comprising: a timing controller and a source driver chip; wherein
the timing controller is configured to: transmit equalization matching data to a source driver chip upon sending a link stable pattern to the source driver chip, wherein the equalization matching data is configured for the source driver chip to determine a target equalization gain, and perform gain compensation, based on the target equalization gain, on display data from the timing controller; and transmit the display data to the source driver chip in response to a first condition being met, wherein the first condition is that the source driver chip determines the target equalization gain; and
the source driver chip is configured to: receive equalization matching data from a timing controller upon receiving a link stable pattern; determine a target equalization gain by performing automatic equalization based on the equalization matching data; receive display data from the timing controller; and perform gain compensation on the display data based on the target equalization gain;
wherein a number of clock edges in a unit time in a signal for carrying the equalization matching data is greater than a number of clock edges in the unit time in a signal for carrying the link stable pattern, and the number of the clock edges in the unit time in the signal for carrying the link stable pattern is greater than a number of clock edges in the unit time in a signal for carrying clock calibration data, wherein the clock calibration data is transmitted, prior to transmitting the link stable pattern, by the timing controller to the source driver chip.