US 12,118,708 B2
Device and method for detecting defects on wafer
Min-Cheol Kang, Hwaseong-si (KR); Do-Nyun Kim, Seoul (KR); Jaehoon Kim, Seoul (KR); and Woojoo Sim, Hwaseong-si (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR); and SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION, Seoul (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Sep. 2, 2021, as Appl. No. 17/465,179.
Claims priority of application No. 10-2020-0128348 (KR), filed on Oct. 5, 2020.
Prior Publication US 2022/0108436 A1, Apr. 7, 2022
Int. Cl. G06T 7/00 (2017.01); G06N 3/045 (2023.01)
CPC G06T 7/0006 (2013.01) [G06T 7/97 (2017.01); G06T 2207/10061 (2013.01); G06T 2207/20081 (2013.01); G06T 2207/20221 (2013.01); G06T 2207/30148 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A wafer defect inference system comprising:
a test equipment configured to receive a first image obtained by imaging circuit patterns formed on a semiconductor wafer by using a scanning electron microscope and a second image obtained by imaging a layout image of a mask for implementing the circuit patterns on the semiconductor wafer and to combine the first image and the second image to generate a combination image; and
at least one computing device configured to communicate with the test equipment and configured to infer a defect associated with the circuit pattern formed on the semiconductor wafer based on the combination image,
wherein the at least one computing device is configured to:
receive the combination image;
perform machine learning for inferring the defect based on the combination image; and
generate an output image including information about the defect based on the machine learning,
wherein the inferring the defect by performing the machine learning is based on an association between the defect in the circuit pattern and the layout image determined by the machine learning.