| CPC G06F 9/3009 (2013.01) [G06F 9/30047 (2013.01); G06F 9/30145 (2013.01); G06F 9/38 (2013.01)] | 14 Claims |
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1. A multi-threading processor comprising:
a cache including a memory and a controller; and
a core electrically connected to the cache and configured to simultaneously execute and manage a plurality of threads,
wherein the core is configured to:
determine an occurrence of a data hazard for the plurality of threads and stall operations of the plurality of threads;
receive, from the cache, hint information instructing a first thread of the plurality of threads to operate; and
initiate an operation of the first thread based on the hint information while the data hazard for the plurality of threads is maintained,
wherein the core transfers a data access request including address information to the cache, and
wherein the controller of the cache is configured to:
search a cache tag based on the address information to determine whether data corresponding to the address information is stored in the memory; and
transfer the hint information to the core in response to determining that the data corresponding to the address information is stored in the memory.
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