US 12,118,331 B2
Bias unit element with binary weighted charge transfer lines
Martin Kraemer, Mountain View, CA (US); Ryan Boesch, Littlefield, CO (US); and Wei Xiong, Mountain View, CA (US)
Assigned to Ceremorphic, Inc., San Jose, CA (US)
Filed by Ceremorphic, Inc., San Jose, CA (US)
Filed on Feb. 1, 2021, as Appl. No. 17/163,588.
Prior Publication US 2022/0244915 A1, Aug. 4, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 7/544 (2006.01); G06F 17/16 (2006.01); H03K 19/20 (2006.01); H03M 1/38 (2006.01)
CPC G06F 7/5443 (2013.01) [G06F 17/16 (2013.01); H03K 19/20 (2013.01); H03M 1/38 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A Bias Unit Element (UE) receiving an E digital input with an enable bit and generating charge coupled to a charge transfer bus comprising charge transfer lines, each charge transfer line having an associated weight, the Bias UE comprising:
a plurality of logic gates, each logic gate having an input coupled to an E digital input bit and the enable bit and generating a positive output and a negative output;
the positive output coupled through a first charge transfer capacitor to a positive charge transfer line, the negative output coupled through a second charge transfer capacitor to a negative charge transfer line;
each charge transfer line having an associated binary weight, the binary weight for each charge transfer line including at least weights 1, 2, 4, 8, and 16.