US 12,118,330 B1
Low power multiplier with non-linear polar material based reset mechanism with sequential reset
Amrita Mathuriya, Portland, OR (US); Rafael Rios, Austin, TX (US); Ikenna Odinaka, Durham, NC (US); Rajeev Kumar Dokania, Beaverton, OR (US); and Sasikanth Manipatruni, Portland, OR (US)
Assigned to Kepler Computing Inc., San Francisco, CA (US)
Filed by Kepler Computing Inc., San Francisco, CA (US)
Filed on Oct. 1, 2021, as Appl. No. 17/449,786.
Application 17/449,786 is a continuation of application No. 17/449,748, filed on Oct. 1, 2021.
This patent is subject to a terminal disclaimer.
Int. Cl. H03K 19/00 (2006.01); G06F 7/501 (2006.01); G06F 7/523 (2006.01); H03K 19/20 (2006.01)
CPC G06F 7/523 (2013.01) [G06F 7/501 (2013.01); H03K 19/0013 (2013.01); H03K 19/20 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a 1-bit full adder comprising a majority gate or a minority gate, wherein the 1-bit full adder comprises non-linear polar material; and
a reset mechanism comprising logic to condition first terminals of a set of capacitors of the 1-bit full adder, the set of capacitors comprising the non-linear polar material, wherein the reset mechanism is to reset second terminals of the set of capacitors sequentially during a reset phase separate from an evaluation phase.