US 12,118,329 B2
Dual capacitor mixed signal mutiplier
Mingu Kang, Old Tappan, NJ (US); Seyoung Kim, White Plains, NY (US); and Kyu-Hyoun Kim, Chappaqua, NY (US)
Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed by INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed on Jan. 16, 2020, as Appl. No. 16/744,824.
Prior Publication US 2021/0224036 A1, Jul. 22, 2021
Int. Cl. G06N 3/02 (2006.01); G06F 7/523 (2006.01); G06N 3/065 (2023.01); G11C 27/02 (2006.01)
CPC G06F 7/523 (2013.01) [G06N 3/065 (2023.01); G11C 27/026 (2013.01); G06N 3/02 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A mixed signal multiplier, comprising:
a sampling capacitor;
a sampling switch configured to apply an input analog value to the sampling capacitor when a digital bit value of a digital signal is one and to apply a zero when the digital bit value of the digital signal is a zero;
an accumulate capacitor;
an accumulate switch configured to store an average of a stored value of the sampling capacitor and a previous stored value of the accumulate capacitor; and
a processor configured to alternately trigger the sampling capacitor and the accumulate capacitor for each bit value in the digital signal to generate a product of the analog value and the digital signal.