US 12,118,287 B2
Automatic generation of sub-cells for an analog integrated circuit
Chih-Chiang Chang, Taipei (TW); Wen-Shen Chou, Hsinchu (TW); Yung-Chow Peng, Hsinchu (TW); Yung-Hsu Chuang, Hsinchu (TW); Yu-Tao Yang, Hsinchu (TW); and Bindu Madhavi Kasina, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Aug. 10, 2023, as Appl. No. 18/447,916.
Application 18/447,916 is a continuation of application No. 17/815,095, filed on Jul. 26, 2022, granted, now 11,816,414.
Application 17/815,095 is a continuation of application No. 17/212,499, filed on Mar. 25, 2021, granted, now 11,429,775, issued on Aug. 30, 2022.
Prior Publication US 2024/0078370 A1, Mar. 7, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 30/392 (2020.01); G06F 30/398 (2020.01); G06F 30/31 (2020.01); G06F 119/18 (2020.01)
CPC G06F 30/392 (2020.01) [G06F 30/398 (2020.01); G06F 30/31 (2020.01); G06F 2119/18 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A method of fabricating an analog integrated circuit, the method comprising:
receiving partition information for the analog integrated circuit, wherein the partition information defines types of sub-cells within the analog integrated circuit, each of the types of sub-cells having a corresponding size and functionality and wherein the corresponding size and functionality both vary between the types of sub-cells;
determining, based on the partition information, first cut locations along a first direction and second cut locations along a second direction of a non-final layout of the integrated circuit, the first direction and the second direction being orthogonal to each other;
partitioning the non-final layout into a plurality of sub-cells based on the first cut locations and the second cut locations; and
merging the plurality of sub-cells to produce a layout diagram of the analog integrated circuit.