US 12,118,282 B2
Removal of hardware intellectual property and programmable replacement
Swarup Bhunia, Gainesville, FL (US); Abdulrahman Alaql, Gainesville, FL (US); Nij Dorairaj, Santa Clara, CA (US); and David Kehlet, Santa Clara, CA (US)
Assigned to University of Florida Research Foundation, Incorporated, Gainesville, FL (US); and Intel Corporation, Santa Clara, CA (US)
Filed by University of Florida Research Foundation, Incorporated, Gainesville, FL (US); and Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 15, 2021, as Appl. No. 17/551,318.
Claims priority of provisional application 63/199,333, filed on Dec. 21, 2020.
Prior Publication US 2022/0198108 A1, Jun. 23, 2022
Int. Cl. G06F 30/327 (2020.01); G06F 9/448 (2018.01); G06F 30/34 (2020.01); G06F 119/06 (2020.01)
CPC G06F 30/327 (2020.01) [G06F 9/4498 (2018.02); G06F 30/34 (2020.01); G06F 2119/06 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A computer-implemented method comprising:
generating, using one or more processors, a control and data flow graph (CDFG) representing a hardware IP design, the CDFG comprising a plurality of control paths and/or data paths;
performing, using the one or more processors, an entropy analysis of the CDFG to determine an entropy measure for each of the plurality of control paths and/or data paths, the entropy measure representing a complexity of an associated control path or an associated data path;
identifying, using the one or more processors, a subset of control paths and/or data paths for removal from the hardware IP design based at least in part on the entropy measure for each of the plurality of control paths and/or data paths;
generating, using the one or more processors, a reduced design based at least in part on: (i) replacing control logic of the hardware IP design represented by each control path of the subset of control paths and/or data paths for removal with first reconfigurable logic, and (ii) replacing data path logic of the hardware IP design represented by each data path of the subset of control paths and/or data paths with second reconfigurable logic; and
providing, using the one or more processors, access to the reduced design.