US 12,118,239 B2
Memory system and operating method supporting fast boot using host memory buffer and default enabled information
Jeong Hyun Kim, Gyeonggi-do (KR); Byong Woo Ryu, Gyeonggi-do (KR); Ji Hun Choi, Gyeonggi-do (KR); Son Hong Min, Gyeonggi-do (KR); and Sung Ju Yoo, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Sep. 27, 2023, as Appl. No. 18/475,205.
Application 18/475,205 is a continuation of application No. 17/575,089, filed on Jan. 13, 2022, granted, now 11,803,322.
Claims priority of application No. 10-2021-0057295 (KR), filed on May 3, 2021; application No. 10-2021-0078335 (KR), filed on Jun. 16, 2021; and application No. 10-2021-0118776 (KR), filed on Sep. 7, 2021.
Prior Publication US 2024/0020052 A1, Jan. 18, 2024
Int. Cl. G06F 3/06 (2006.01); G06F 13/16 (2006.01)
CPC G06F 3/0656 (2013.01) [G06F 3/0625 (2013.01); G06F 3/0679 (2013.01); G06F 13/1668 (2013.01); G06F 13/1673 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A memory system comprising:
a memory device capable of storing data; and
a memory controller configured to communicate with the memory device to control the memory device,
wherein the memory controller is configured to receive, from a host in communication with the memory system, information indicating whether the host maintains a configuration of a host memory buffer in the host and target data stored in the host memory buffer when the memory system is in a low power mode state,
wherein the memory controller is further configured to:
determine a target time which is a time point at which the memory system accesses the target data after waking up from the low power mode state as a time point at which a communication link between the host and the memory system is accessible when the host maintains the configuration of the host memory buffer and the target data stored in the host memory buffer.