| CPC G06F 3/0632 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0679 (2013.01)] | 20 Claims |
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1. A semiconductor memory device comprising:
a memory cell array that includes a plurality of memory cell rows designated by row addresses, each of the plurality of memory cell rows including a plurality of memory cells;
a row hammer management circuit that includes a hammer address queue and is configured to:
automatically store random count data in count cells of each of the plurality of memory cell rows during a power-up sequence of the semiconductor memory device; and
determine counted values by counting a number of times of access associated with each of the plurality of memory cell rows in response to an active command from an external memory controller and store the counted values in the count cells of each of the plurality of memory cell rows as count data,
wherein the hammer address queue is configured to:
store one or more of the row addresses up to a first number based on a comparison of the counted values with a reference number of times, the one or more of the row addresses being candidate hammer addresses; and
output one of the candidate hammer addresses stored therein as a hammer address; and
a refresh control circuit configured to receive the hammer address and perform a hammer refresh operation on one or more of the plurality of memory cell rows that are physically adjacent to a memory cell row that corresponds to the hammer address.
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