US 12,118,220 B2
Elastic persistent memory regions
Joseph H. Steinmetz, Loomis, CA (US); Luca Bert, San Jose, CA (US); and William Akin, Morgan Hill, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on May 23, 2023, as Appl. No. 18/200,685.
Application 18/200,685 is a continuation of application No. 17/232,971, filed on Apr. 16, 2021, granted, now 11,704,029.
Prior Publication US 2023/0297256 A1, Sep. 21, 2023
Int. Cl. G06F 3/06 (2006.01); G06F 12/0808 (2016.01)
CPC G06F 3/0631 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0644 (2013.01); G06F 3/068 (2013.01); G06F 12/0808 (2013.01); G06F 2212/1044 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A system comprising:
a memory; and
at least one processing device, operatively coupled to the memory, to perform operations comprising:
causing a region of a non-volatile memory device to be accessible through a persistent memory region (PMR) of a volatile memory device, wherein the PMR utilizes a power protection mechanism to prevent data loss in an event of power loss; and
managing PMR caching with respect to the PMR by using a caching mechanism that manages page eviction based on a set of key registers.