US 12,117,952 B2
Multi-path server and multi-path server signal interconnection system
Xiangtao Kong, Jinan (CN)
Assigned to Shandong Yingxin Computer Technologies Co., Ltd., Jinan (CN)
Appl. No. 18/276,413
Filed by Shandong Yingxin Computer Technologies Co., Ltd., Jinan (CN)
PCT Filed Sep. 28, 2021, PCT No. PCT/CN2021/121428
§ 371(c)(1), (2) Date Aug. 8, 2023,
PCT Pub. No. WO2022/179105, PCT Pub. Date Sep. 1, 2022.
Claims priority of application No. 202110205309.4 (CN), filed on Feb. 24, 2021.
Prior Publication US 2024/0045821 A1, Feb. 8, 2024
Int. Cl. G06F 13/40 (2006.01)
CPC G06F 13/4022 (2013.01) 19 Claims
OG exemplary drawing
 
1. A multi-path server, comprising a first circuit, a second circuit, a third circuit, and a fourth circuit, each of the four circuits comprising a Platform Controller Hub configured to output Power Management Synchronization signals when in place, an extended module connected to the Platform Controller Hub and configured to extend the Power Management Synchronization signal into multiple paths, a switch module connected to the extended module, and two CPUs connected to the switch module, wherein
an extended module in the first circuit is connected to a switch module in the second circuit, a switch module in the third circuit, and a switch module in the fourth circuit, an extended module in the third circuit is connected to a switch module in the fourth circuit; and
after a switch module and a Platform Controller Hub in each said circuit receive a target partition instruction, the switch module performs switching action according to the target partition instruction, and the Platform Controller Hub performs in-place action according to the target partition instruction, such that each said circuit forms a target partition corresponding to the target partition instruction, and the Power Management Synchronization signals are interconnected in the target partition through a corresponding CPU; the target partition comprises a single partition, a secondary partition, and a quarter partition;
wherein the third switch group comprises a first multi-path multiplexer and a second multi-path multiplexer, a first terminal of the first multi-path multiplexer and a first terminal of the second multi-path multiplexer are used as a first terminal of the third switch group, the first terminal of the first multi-path multiplexer is connected to a third terminal of a fourth analog switch in a computing board in which the first multi-path multiplexer is located, a first terminal of the second multi-path multiplexer is connected to a third terminal of a third analog switch in a computing board in which the second multi-path multiplexer is located, a second terminal of the first multi-path multiplexer and a second terminal of the second multi-path multiplexer are used as a second terminal of the third switch group, a third terminal of the first multi-path multiplexer and a third terminal of the second multi-path multiplexer are used as a third terminal of the third switch group, and a fourth terminal of the first multi-path multiplexer and a fourth terminal of the second multi-path multiplexer are used as a fourth terminal of the third switch group;
a third terminal and a fourth terminal of the first multi-path multiplexer in the second computing board are connected to a third output terminal of a first extender in the first computing board, and a third terminal and a fourth terminal of the second multi-path multiplexer in the second computing board are connected to a fourth output terminal of a first extender in the first computing board;
a third terminal of a first multi-path multiplexer in the third computing board is connected to a first output terminal of a second extender in the first computing board, and a third terminal of a second multi-path multiplexer in the third computing board is connected to a second output terminal of a second extender in the first computing board; and
a third terminal of a first multi-path multiplexer in the fourth computing board is connected to a third output terminal of a second extender in the first computing board, a fourth terminal of a first multi-path multiplexer in the fourth computing board is connected to a third output terminal of a first extender in the third computing board, a third terminal of a second multi-path multiplexer in the fourth computing board is connected to a fourth output terminal of a second extender in the first computing board, and a fourth terminal of a second multi-path multiplexer in the fourth computing board is connected to a fourth output terminal of a second extender in the third computing board.