US 12,117,945 B2
Memory controller with pseudo-channel support
Hideki Kanayama, San Jose, CA (US); and YuBin Yao, Shanghai (CN)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed on Jun. 24, 2022, as Appl. No. 17/849,117.
Prior Publication US 2023/0418772 A1, Dec. 28, 2023
Int. Cl. G06F 13/16 (2006.01)
CPC G06F 13/1689 (2013.01) [G06F 13/1621 (2013.01); G06F 13/1642 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A data processor for accessing a memory having a first pseudo channel and a second pseudo channel, comprising:
at least one memory accessing agent for generating a memory access request;
a memory controller for providing memory commands to the memory in response to a normalized request selectively using a first pseudo channel pipeline circuit and a second pseudo channel pipeline circuit, wherein each of the first and second pseudo channel pipeline circuits re-orders and prioritizes accesses based on particular access patterns in its respective pseudo channel;
a data fabric coupled between said at least one memory accessing agent and said memory controller for converting said memory access request into said normalized request selectively for said first pseudo channel pipeline circuit and said second pseudo channel pipeline circuit; and
a serializer that is operable to serialize memory commands from said first pseudo channel pipeline circuit and said second pseudo channel pipeline circuit.