US 12,117,935 B2
Technique to enable simultaneous use of on-die SRAM as cache and memory
Chintan S. Patel, Santa Clara, CA (US); Vydhyanathan Kalyanasundharam, Santa Clara, CA (US); Benjamin Tsien, Santa Clara, CA (US); and Alexander J. Branover, Boxborough, MA (US)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed on Jun. 28, 2022, as Appl. No. 17/852,300.
Prior Publication US 2023/0418745 A1, Dec. 28, 2023
Int. Cl. G06F 12/00 (2006.01); G06F 12/0802 (2016.01)
CPC G06F 12/0802 (2013.01) [G06F 2212/60 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A method for operating a cache, the method comprising:
utilizing a first portion of the cache as a cache; and
reconfiguring a first sub-portion of the first portion to be accessed directly, the reconfiguring including invalidating entries of the first sub-portion.