US 12,117,903 B2
FPGA acceleration system for MSR codes
Mian Qin, College Station, TX (US); Joo Hwan Lee, San Jose, CA (US); Rekha Pitchumani, Fairfax, CA (US); and Yang Seok Ki, Palo Alto, CA (US)
Assigned to SAMSUNG ELECTRONICS CO., LTD., (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Jul. 17, 2023, as Appl. No. 18/223,019.
Application 18/223,019 is a continuation of application No. 17/367,315, filed on Jul. 2, 2021, granted, now 11,726,876.
Application 17/367,315 is a continuation of application No. 16/271,777, filed on Feb. 8, 2019, granted, now 11,061,772, issued on Jul. 13, 2021.
Claims priority of provisional application 62/780,185, filed on Dec. 14, 2018.
Prior Publication US 2023/0367675 A1, Nov. 16, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 11/10 (2006.01); G06F 13/28 (2006.01)
CPC G06F 11/1076 (2013.01) [G06F 13/28 (2013.01)] 17 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a host interface circuit configured to receive first instruction, wherein the first instruction instructs the apparatus to perform computations associated with data elements stored by a storage system;
a memory interface circuit configured to receive the data elements from a storage system; and
computation circuit configured to perform at least a portion of the computations, wherein the computation circuit is configurable based upon a number of data nodes associated with the data elements, and wherein the data nodes comprise storage devices.