US 12,117,902 B2
Memory system
Kengo Kurose, Tokyo (JP); Masanobu Shirakawa, Kanagawa (JP); and Marie Takada, Kanagawa (JP)
Assigned to KIOXIA CORPORATION, Tokyo (JP)
Filed by KIOXIA CORPORATION, Tokyo (JP)
Filed on May 26, 2023, as Appl. No. 18/324,226.
Application 18/324,226 is a continuation of application No. 17/718,969, filed on Apr. 12, 2022, granted, now 11,698,834.
Application 17/718,969 is a continuation of application No. 17/092,054, filed on Nov. 6, 2020, granted, now 11,334,432, issued on May 17, 2022.
Application 17/092,054 is a continuation of application No. 16/550,355, filed on Aug. 26, 2019, granted, now 10,866,860, issued on Dec. 15, 2020.
Claims priority of application No. 2019-051530 (JP), filed on Mar. 19, 2019.
Prior Publication US 2023/0297473 A1, Sep. 21, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 11/10 (2006.01); G11C 11/56 (2006.01); G11C 16/04 (2006.01); G11C 16/26 (2006.01)
CPC G06F 11/1068 (2013.01) [G11C 11/5642 (2013.01); G11C 11/5671 (2013.01); G11C 16/0483 (2013.01); G11C 16/26 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A memory system comprising:
a semiconductor memory including a word line and a plurality of memory cells connected to the word line; and
a memory controller configured to write data in the memory cells, wherein the memory controller configured to:
read data of the memory cells as first data;
perform error correction on the first data; and
determine whether or not to perform a refresh operation of a block based on a number of error bits of the first data, a first number and a second number, the first number representing a number of bits each of which has different values in a first manner between the first data and first expected data obtained by the error correction on the first data, the second number representing a number of bits each of which has different values in a second manner between the first data and the first expected data, the block having the memory cells.